On the Development of a Fast and Accurate Bridging Fault Simulator

This paperpresent~ an alternative modeling and simulation method for CMOS bridging faults. The significance of the method is the introduction of a set of unique-bridge tables which characterize the bridged outputs for each bridge and a set of unique-cell tables which characterize how each cell interprets an analog input. These two sets of tables are derived dynamically for a specific design by using a SPICE circuit simulator first. Then they can later be used by any logic fault simulator to simulate bridging faults. In this way, the proposed method can perform very fast bridging fault simulation and yet with SPICE accuracy. The paper shows how these two sets of tables are derived and used in a parallel pattern fault simulator. Experimental results on ISCASR5 benchmarks are promising. keywords: defect, bridging fault, fault modeling, testing, fault simulation Addresss of the authors: Section of Design of Electronic Systems(ES) Faculty of Electrical Engineering Eindhoven University of Technology P.O. Box 513, 5000 MB, Eindhoven, The Netherlands Tels. +31-(0)40-473373, +31-(0)40-473710 Fax +31-(0)40-404527 Email [email protected]@es.ele.tue.nl